The present invention relates to semiconductor integrated circuits and, more specifically, to test structures for testing linearity of delay lines fabricated on integrated circuits.
Semiconductor integrated circuits often include two or more delay lines, such as one master delay line and several slave delay lines. Each delay line is typically constructed of a number of unit delays that are connected together in series. In a programmable delay line, the delay line has a control input which determines the number of unit delays through which the input signal passes.
Linearity between different delay lines on the same integrated circuit is very important for correct operation of the circuit. Linearity means that each unit delay in one delay line has the same delay as each unit delay in another delay line. If the delay lines have good linearity, the delay through one delay line increases by the same amount as the delay through another delay line for additional unit delay added to the line by the control input.
One example of a circuit in which delay lines having good linearity are needed is a delay-locked loop (xe2x80x9cDLLxe2x80x9d) that drives one or more slave delay lines. DLLs are used in integrated circuits for removing phase differences between clocks, such as phase differences caused by propagation delay. A DLL is constructed with a master delay line and outputs a delay value. If, for example, the circuit designer wants one of the slave delay lines to have a delay equal to half a clock period, the circuit designer programs the slave delay line with the delay value divided by two. In this way, the delay through the slave delay line can be calibrated to remove variations in process, voltage and temperature since the delay value produced by the DLL varies to remove these factors. In order for this calibration to be accurate, the master delay line in the DLL must have good linearity with respect to the slave delay line. Non-linearity will consume timing margin where the output of the slave delay line is used.
In order to maximize linearity, the physical layout of the unit delays in each delay line is typically the same. Therefore, when the delay lines are fabricated, each unit delay has the same physical structure. However, fabrication tolerances can lead to variances between one unit delay and the next even though each unit delay is built with the same structure. Since linearity of delay lines is so important for the correct operation of an integrated circuit, there exists a need to test linearity of delay lines easily in a short period of time during production.
One method of testing linearity is to measure the entire delay through each delay line. However, this approach may hide linearity errors. For example if one unit delay within a delay line has a delay that is 50% larger than expected and another unit delay in the delay line has a delay that is 50% less than expected, then these two errors cancel one another and cannot be measured with the old approach. Accumulated errors can therefore hide unit delay errors with the old approach.
Improved methods and test structures are desired for testing linearity between two or more delay lines on an integrated circuit.
One embodiment of the present invention is directed to a method for testing linearity of two or more programmable delay chains in an integrated circuit. A first delay chain is successively programmed to a first sequence of delay settings and, for each delay setting in the first sequence, a second delay chain is successively programmed to a second sequence of delay settings. The second sequence sweeps a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay. For each delay setting of the second delay chain, a logic transition is applied to inputs of the first and second delay chains and the output of one of the first and second delay chains is latched as a function of the output of the other of the first and second delay chains to produce a sample value. The sample values produced for each delay setting in the first sequence are monitored to determining whether the logic transition occurs in the sample values within an expected time window.
Another embodiment of the present invention is directed to a delay line linearity test structure fabricated in an integrated circuit. The test structure includes first and second delay chains, a latch, a memory, a logic transition generator and a control circuit. Each delay line is programmable to a plurality of different delay settings and includes a signal input and a signal output. The latch has a data input coupled to the output of one of the first and second delay lines, a latch control coupled to the output of the other of the first and second delay lines, and a latch output. The control circuit successively programs the first delay chain to a first sequence of the delay settings. For each delay setting in the first sequence, the control circuit successively programs the second delay chain to a second sequence of the delay settings that sweep a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay. The logic transition generator applies a logic transition to the inputs of the first and second delay chains for each of the delay settings of the first and second delay chains. The memory is coupled to the latch output for storing a sample value produced on the latch output in response to the logic transition for each delay setting of the second delay chain. The control circuit determines whether the logic transition occurs within an expected time window in the sample values stored in the memory for each delay setting in the first sequence.
Another embodiment of the present invention is directed to a delay line linearity test structure fabricated in an integrated circuit. The test structure includes first and second delay chains, wherein each delay line is programmable to a plurality of different delay settings and includes a signal input and a signal output. A control circuit successively programs the first delay chain to a first sequence of the delay settings and successively programs the second delay chain to a second sequence of the delay settings that sweep a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay, for each delay setting in the first sequence. The control circuit applies a logic transition to the signal inputs of the first and second delay chains and latches the signal output of one of the first and second delay chains as a function of the signal output of the other of the first and second delay chains to produce a sample value, for each delay setting of the second delay chain. The control circuit then determines whether the logic transition occurs within an expected time window in the sample values produced for each delay setting in the first sequence.